This invention relates to a clock recovery circuit for a digital demodulator of the type comprising means for multiplying an input signal with first and second orthogonal demodulation reference signals to generate respective product signals, means for integrating the product signals to generate first and second integrated values indicative of digital data encoded in the input signal, and means for digitizing the integrated values to generate first and second digital values
Digital demodulators of the general type described above are well known to those skilled in the art, as for example in Quadrature Amplitude Modulation (QAM) systems. Typically, a plurality of separate component signals are combined to form a composite signal which is transmitted on a single signal channel, and each signal is orthogonal to the others and is amplitude modulated. When the received composite signal is multiplied by an appropriate local oscillator signal and the resulting product is integrated over an integral number of symbol periods, the resulting integration is indicative of the amplitude of a respective one of the component signals of the composite signal.
"Offset Quadrature Communications with Decision-Feedback Carrier Synchronization" (Marvin K. Simon and Joel G. Smith, IEEE Transations on Communications Volume Com-22 No. 10, Oct. 1974, Pages 1576-1584) discloses a related offset quadrature phase shift keyed system which utilizes a voltage controlled oscillator to generate the local oscillator signals. The frequency and phase of this oscillator are controlled in a feedback loop. The oscillator generates demodulation reference signals which are multiplied with the incoming signal in multipliers. The resulting products are integrated and then quantized to produce two digitized values. As shown in FIG. 3 of the Simon ,e/uns/et al./ article, the feedback loop for the voltage controlled oscillator includes two feedback signals which are summed to create a control signal e(t). Each of these feedback signals is generated as the product of the digitized value of one channel with the delayed product value of the other channel.
This approach places considerable demands on the multipliers. Since the analog input channel of each multiplier receives the product value from a respective channel, each multiplier must remain linear over a considerable range of product values. Such multipliers, though possible to create, can be undesirably expensive in many applications.
It is a primary object of the present invention to provide an improved clock recovery system which reduces the range of analog inputs to such multipliers in clock recovery feedback loops, and thereby reduces the complexity and the cost of the hardware required to implement the system.